1. Field of the Invention
The invention relates to an automated system and method for distinguishing dummy features from main features on a mask layer, thereby effectively using resource and cycle time.
2. Description of the Related Art
A typical wafer for an integrated circuit (IC) includes multiple layers formed on a substrate. These layers, each layer having a predetermined pattern thereon, can result in an uneven topography on the wafer surface. An uneven topography on one layer can have adverse effects on one or more subsequent layers.
For example, FIG. 1A illustrates a cross-section of an etched layer 100 on a wafer, wherein etched layer 100 includes two features 101 and 102. Feature 101 extends above a level 103, i.e. a protrusion, whereas feature 102 extends below level 103, i.e. an intrusion. If another layer 104 is formed on etched layer 100, as shown in FIG. 1B, layer 104 can also have an uneven surface due to the uneven topography of layer 100. The uneven surface of layer 104 can undesirably complicate lithographic processing on this layer because of light reflection or inadequate coverage over the “steps” in layer 100.
A common technique used to counter the effects of an uneven topography is planarization. The goal of planarization is to ensure that subsequent lithographic results are independent from or, more realistically, much less dependent on the underlying wafer topography from previous layers. Planarization is especially important for layers requiring critical dimension control. Specifically, an uneven topography could pose significant depth of focus problems, thereby rendering CD control across the wafer virtually impossible.
However, planarization itself can cause problems on the wafer. For example, in one known planarization process shown in FIG. 1C, a thick spin-on-glass (SOG) layer 105 can be formed on etched layer 100. After formation, SOG layer 104 is baked, thereby leaving substantially planarized silicon dioxide. The resulting surface, although significantly more even than layer 104, still retains irregularities that can influence a subsequent lithographic process. For this reason, a chemo-mechanical polish (CMP) can be used to polish SOG layer 105.
In a CMP process, a device mechanically polishes the surface of the wafer. Unfortunately, because of the underlying features in layer 100, such as features 101 and 102, the polishing of layer 105 can result in an uneven force being applied to certain areas of the surface of the wafer. In turn, this uneven force can cause some mechanical stress or even bowing of the wafer, thereby resulting in uneven polishing of the surface. FIG. 1D illustrates a recessed area 106 that could result from a CMP of layer 105.
To prevent such recesses, dummy pillars can be placed on regions of the wafer where geometry density is low, thereby providing mechanical support during a CMP and thus preventing uneven polishing. For example, FIG. 2 illustrates a top-level view of a layer 200 including two main features 201 and 202 and dummy pillars 203 and 204. The process of introducing these dummy pillars (hereinafter dummy features) is often referred to as “dummification”.
During the mask design process, dummy features 203–204 are added after the layout design of main features 201–202. Of importance, a GDS-II file for a mask layer can include multi-level information, thereby allowing main features 201–202 to be distinguishable from dummy features 203–204. However, this design information can then be mapped into a mask data preparation (MDP) language, which is a one-level file. In one embodiment, this mapping can be performed by the CATS™ tool, which is licensed by the assignee of the invention. Thus, after layout, dummy features 203–204 and main features 201–202 are effectively treated as one type of data. As a consequence, post-layout processing is applied globally to all features including the dummy features instead of selectively to only the main features. Examples of post-layout processes can include optical proximity correction (OPC), placement of phase shifting structures, mask writing, mask fabrication, mask inspection, and mask defect correction.
Applying such post-layout processes globally can result in wasted resources and cycle time. In some cases, unnecessary processing of dummy or other less important features can take up a significant portion or even the majority of the manufacturing cycle. Therefore, a need arises for a system and method of identifying features on a mask layer for post-layout processing.